SRAM (static random access memory), which contains a memory cell including four transistors, is known as a semiconductor memory device. Hereinafter, SRAM containing a memory cell of four transistors will be denoted as 4T-SRAM.
In 4T-SRAM, when a memory cell holds data (holding state), a bit line needs to be maintained at an “H” (High) level (hereinafter, denoted as H). A precharge circuit is used to precharge the bit line to “H”. The precharge circuit includes a p-channel MOS field effect transistor (hereinafter, denoted as a pMOS transistor). The bit line is maintained, as described above, at “H” in a holding state of data and thus, a power supply voltage (“H”) is supplied to the source of a pMOS transistor in the precharge circuit, the voltage “H” of the bit line is supplied to the drain, and an “L” (Low) level (hereinafter, denoted as L) is supplied to the gate. At this point, a gate leak current arises in the pMOS transistor from a channel region between the source and drain to the gate via a gate insulating film.